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AN-895

Rev. 0 | Page 7 of 16

C IMPLEMENTATION ON THE ADUC702x SERIES

MICROCONVERTER

The ADuC702x series of parts contain two full hardware master

and slave I

C ports. These ports support up to four addresses

each and have configurable interrupts that allow the serial

EEPROM commands to be implemented.

At a basic level, the I

C hardware interface behaves like a

standard UART. There are receive and transmit buffers each of

which consists of 2-byte FIFOs. This application note describes

in detail the four types of communication (master/slave

receive/transmit) and the use of the FIFO.

Use of the FIFO

There are four 2-byte FIFOs per I

C block:

• Master receive

• Master transmit

• Slave receive

• Slave transmit

The following sections describe the transmit FIFO and the

receive FIFO.

Table 1. I2CxFSTA MMR Bit Descriptions

Bit No. Description

31 to 10 Reserved.

9 Master Transmit FIFO Flush.

Set by the user to flush the master Tx FIFO. This bit also flushes the slave receive FIFO.

Cleared automatically once the master Tx FIFO is flushed.

8 Slave Transmit FIFO Flush.

Set by the user to flush the slave Tx FIFO.

Cleared automatically once the slave Tx FIFO is flushed.

7 to 6 Master Rx FIFO Status Bits.

00 FIFO empty

01 Byte written to FIFO

10 1 byte in FIFO

11 FIFO full

5 to 4 Master Tx FIFO Status Bits.

00 FIFO empty

01 Byte written to FIFO

10 1 byte in FIFO

11 FIFO full

3 to 2 Slave Rx FIFO Status Bits.

00 FIFO empty

01 Byte written to FIFO

10 1 byte in FIFO

11 FIFO full

1 to 0 Slave Rx FIFO Status Bits.

00 FIFO empty

01 Byte written to FIFO

10 1 byte in FIFO

11 FIFO full

1 2 3 4 5 6 7 8 9 10 11 12 ... 15 16

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