Enable-IT 895 Series Bedienungsanleitung PDF herunterladen (Seite 5)

AN-895

Rev. 0 | Page 5 of 16

Repeated Start Condition

A repeated start condition occurs when a second start condition

is sent to a slave without a stop condition being sent in between.

This allows the master to reverse the direction of the transfer, by

changing the R/

bit without having to give up control of the bus.

An example of a transfer sequence is shown in

Figure 6. This is

generally used where the first data sent to the part sets up the

An interrupt is generated when a repeated start + slave address

is received. This can be differentiated from a start + slave

address by using the status bits in the I2CxSSTA MMR.

Note that the ADuC702x device cannot directly generate an I

repeated start sequence when in master mode.

If a user has full control of the entire I

C bus, a workaround is

possible by disabling the generation of the stop condition before

the desired second start condition. This is possible using the

following steps:

1. Put a lower value pull-up resistor on the SDA line. For

example, connect SDA to V

via a 4.7 kΩ resistor; connect

SCL to V

via a 20 kΩ resistor.

2. Add the following code sequence:

I2C0CCNT = 0x0; // Sets Start/Stop condition counter value to 0 - minimum value.

I2C0ADR = 0xA0; // Write sequence

I2C0MTX = 0x7; // Load the Tx FIFO

while ((I2C0FSTA & 0x30) != 0x00) {} // Wait for the Tx FIFO to empty

I2C0CNT = 0x1; // Read 2 bytes from the slave

I2C0ADR = 0xA1; // Send out the Read condition

I2C0CCNT = 0x80; // Set the Start/Stop counter to a nonzero value to re-enable the Stop

Condition

MSB

START

BIT

SCL

ACK

BIT

ACK

BIT

SLAVE ADDRESS

SDA

MSBLSB LSB

DATA

1178 8992

3TO 6 2TO 7

R/W

MSB

START

BIT

ACK

BIT

ACK

BIT

STOP

BIT

SLAVE ADDRESS

MSBLSB LSB

DATA

1178 8992

3TO 6 2TO 7

R/W

Figure 6. I

C Repeated Start Sequence

1 2 3 4 5 6 7 8 9 10 ... 15 16

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