Enable-IT 895 Series Bedienungsanleitung PDF herunterladen (Seite 10)

AN-895

Rev. 0 | Page 10 of 16

Slave Receive

As the data is received by an I

C slave, an interrupt is generated

as each byte of data is placed in the receive FIFO, that is, after

the ninth clock of each byte is received. If the FIFO is not read

before a third byte is received, the interface automatically

delivers a NACK for the last data transmitted, and Bit 4 of the

I2CSSTA register is set, indicating a receive FIFO overflow.

To read data from the FIFO, the I2C0RX register is used. Bit 3

of the I2C0SSTA register indicates that the slave has received

data. Only reading I2C0SRX clears this bit. Flushing the FIFO

does not clear Bit 3.

The master automatically sends a stop condition after sending

the last data.

//ENABLE I2C on GPIO P1.0 AND P1.1

GP1CON = 0x22;

//RETURN FROM ISR

VECTOR TO

INTERRUPT SERVICE ROUTINE

//SET UP I2C SLAVE MODE

I2C0CFG = 0x1;

WAIT FOR MASTER

//CHECK FOR R

INTERRUPT

if ((I2C0SSTA AND 0x08) == 0x08)

//READ DATA FROM FIFO

dat[i] = I2C0SRX

//SPECIFY INTERRUPT SERVICE ROUTINE

AND ENABLE SLAVE I2C INTERRUPT

IRQ = MY_IRQ_FUNCTION;

IRQEN = 0x200;

Figure 17. Slave Receive Flowchart

START

DEVICE

ADDRESS

WRITE

WORD ADDRESS (n) DATA (n)

SDA LINE

MSB

LSB

R/W

ACK

LSB

ACK

MSB

ACK

DATA (n + 1)

ACK

DATA (n + x)

STOP

ACK

RECEIVE

INTERRUPT

RECEIVE

INTERRUPT

RECEIVE

INTERRUPT

RECEIVE

INTERRUPT

Figure 18. Example of a Slave Receive

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 16

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