AN-895
Rev. 0 | Page 13 of 16
I
2
C REGISTER DEFINITIONS
The I
2
C peripheral interface consists of 15 registers in total:
• Four registers that include the transmit/receive
master/slave MMR (I2CxSRX, I2CxSTX, I2CxMRX,
I2CxMTX).
• Three status registers that include the master/slave/FIFO
(I2CxMSTA, I2CxSSTA, I2CxFSTA).
• Eight configuration registers that include four slave
addresses, one master address byte, one master clock
divider, one master receive data count, and one I
2
C
configuration register (I2CxID0, I2CxID1, I2CxID2,
I2CxID3, I2CxADR, I2CxDIV, I2CxCNT, I2CxCFG).
• Other registers for general call are not discussed in this
application note.
Four of these registers are described in detail in the following
sections:
• I2CxDIV, the clock divider register.
• I2CxMSTA, the master status register, see
Table 2.
• I2CxCFG, the I
2
C configuration register, see Table 3.
• I2CxSSTA, the slave status register, see
Table 4.
I2CxDIV, Clock Divider Register
This is a 16-bit register containing two 8-bit values, DIVH and
DIVL. The value in this register sets up the speed of the I
2
C bus.
This is set up according to the formula
) (2 )2( DIVLDIVH +++
=
UCLK
kserialcloc
f
f
where:
f
UCLK
is the clock before the clock divider.
DIVH is the high period of the clock.
DIVL is the low period of the clock.
Thus, for 100 kHz operation,
DIVH = DIVL =0xCF (I2C0DIV = 0xCFCF)
and for 400 kHz,
DIVH = 0x28 DIVL = 0x3C (I2C0DIV = 0x283C)
I2CxMSTA: Master Status Register
Table 2. I2CxMSTA MMR Bit Descriptions
Bit No. Description
7 Master Transmit FIFO Flush.
Set by the user to flush the master Tx FIFO. This bit also flushes the slave Rx FIFO.
Cleared automatically once the master Tx FIFO is flushed.
6 Master Busy.
Set automatically if the master is busy.
Cleared automatically.
5 Arbitration Loss.
Set in multimaster mode if another master has the bus.
Cleared when the bus becomes available.
4 No ACK.
Set automatically if there is no acknowledge of the address by the slave device.
Cleared automatically by reading the I2C0MSTA register.
3 Master Receive IRQ.
Set after receiving data.
Cleared automatically by reading the I2C0MRX register.
2 Master Transmit IRQ.
Set at the end of a transmission.
Cleared automatically by writing to the I2C0MTX register.
1 Master Transmit FIFO Underflow.
Set automatically if the master transmit FIFO is underflowing.
Cleared automatically by writing to the I2C0MTX register.
0 Master Tx FIFO Empty.
Set automatically if the master transmit FIFO is empty.
Cleared automatically by writing to the I2C0MTX register.
(14 Seiten)
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