
Hytec Electronics Ltd 8424TR/UTM/G/20/2.0
Page 20
7.7 Pre-Trigger Delay Register (PTD)
Read/write Address: 64hex
The PTD allows a pre-trigger delay to be programmed in to the module that will effect all channels. The
time delay in seconds is calculated by using the following formula:
Time Delay(s) = (10 / Digitisation Rate) × PTD Value.
PTD Value= (Time Delay Required(s) x Scanning Rate)/10.
If the unit is stopped by either the software stop or the External stop bit when the stop bit is released the
pre-trigger delay will be indicated.
Note: This register should be set to zero when in VT mode to avoid confusion with results.
7.8 Voltage Trigger Mode
The voltage trigger mode (VT=1 and TR=1) allows the unit to wait after it is triggered (software or
hardware) for the selected input signal to reached the lower threshold value before acquiring data in to the
memory. The digitised values will be log in to memory for the programmed number of samples before
stopping.
7.8.1 Pre Voltage Trigger Buffer
In this mode a pre voltage trigger buffer can be set up in the memory. Here the signal is digitised in to a
circulating buffer until the signal reaches the lower threshold value. The memory pointer is then set to
the end of the pre trigger memory buffer and logging carries on until the end of the memory is reached or
the set number of sample has been logged.
Important Note
When setting the NOC in VT mode must take in to account the pre voltage trigger memory size. i.e. if put
0x1000 in to pre trigger memory buffer register will need to put 0x40000-0x1000 in to NCO register to
ensure the memory does not wrap round and over write the pre trigger memory buffer.
7.9 Pre Voltage Trigger Memory Buffer Size Register
Read/write Address: 64hex
This set the size of the pre voltage trigger memory circulating buffer size when set in Voltage Trigger
mode (VT).
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
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