Enable-IT 8424 Bedienungsanleitung Seite 19

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Hytec Electronics Ltd 8424TR/UTM/G/19/2.0
Page 19
7.4 Lower Time Stamp Registers
Read/write Address: Chan 1=30&32hex, Chan 2=3E&40hex, Chan 3=4C&4Ehex, Chan 4=5A&5Chex.
When the data exceeds the pre-set value of the Lower Threshold register the current contents of the
Conversion Pointer register (CPR) is store in the Lower Threshold Time Stamp register.
Once the LTH is reached for the first time the address is logged. It will not log a new address if the signal
goes below then back above LTH value.
If the unit is stopped either by the Ext Stop or Software Stop signals the time stamp register is cleared.
When the stop signal is removed a new value will be logged when the threshold is reached.
Lower word
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
LTS15
LTS14
LTS13
LTS12
LTS11
LTS10
LTS9
LTS8
LTS7
LTS6
LTS5
LTS4
LTS3
LTS2
LTS1
LTS0
Upper word
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
x x x x x x x x x x x x x x LTS17
LTS16
7.5 Upper Time Stamp Registers
Read/write Address: Chan 1=34&36hex, Chan 2=42&44hex, Chan 3=50&52hex, Chan 4=5E&60hex.
The Upper Threshold Time Stamp register (UTTS) will not be active until the Lower Threshold has been
reached.
The Upper Threshold Time Stamp register (UTTS) register is updated when ever the data falls below the
Upper Threshold limit and the Lower Threshold limit has been reached.
The UTTS is cleared if the peak voltage is up dated (i.e. peak value not yet reached) once the peak value
has been reached and the Upper Threshold limit attained UTTS is logged.
Lower word
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
UTS15
UTS14
UTS13
UTS12
UTS11
UTS10
UTS9 UTS8 UTS7 UTS6 UTS5 UTS4 UTS3 UTS2 UTS1 UTS0
Upper word
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
x x x x x x x x x x x x x x UTS17
UTS16
7.6 Peak Value Registers
Read Address: Chan 1=38hex, Chan 2=46hex, Chan 3=54hex, Chan 4=62hex.
These four registers hold the positive peak values the data reached for each channel during acquisition.
These registers are read only registers and are cleared when ever the module is reARMed.
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