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Hytec Electronics Ltd 8424TR/UTM/G/13/2.0

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5.4 Interrupt Vector

Read/write Address: 8hex

The vector register is a 16 bit register which stores the interrupt vector value.

D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

V15 V14 V13 V12 V11 V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0

5.5 Extended Control & Status Register (CSR Ext)

Read/write Address: Ahex

D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

CAL

BTE

TE E EFW

IFW R Cont

ISE IS SMI TEN

TEN This shows the trigger status of the unit (Read only).

SMI This sets Software Memory Inhibit when at logic ‘1’. This does not generate an interrupt or set

the MIS in the CSR.

IS ADC Register update status. Set when the ADC Registers have been updated. Generates IRQ0* if

set and ISE is set to a logic 1.

ISE Enables interrupt when ADC Registers have been updated.

CONT If set to ‘1’ then will allow multiple triggers in CC mode. On each trigger the Sample clock is

restarted. A max delay of 100ns between Trigger and the first conversion is guaranteed.

R Set ADC range set to 0 = +/-10V and range set to 1 = +/-5V.

IFW Do not set this bit as setup and calibration data maybe lost. This bit enables the

FPGA flash write from buffer command

EFW Do not set this bit as setup and calibration data maybe lost. This bit enables the

External flash write by writing to IP mem i.e. switches off RAM

E Do not set this bit as setup and calibration data maybe lost. This bit enables the

External flash chip or sector erase when do a IP write to mem. If IP data is 0x10 then

chip erase (64s time taken) if IP data is 0x30 then sector erase where the sector

address is given in the IP memory address lines. If chip erase then IP mem address =

0x555 and data 0x10.

TE When set to '0' = Ext Trigger on rising edge when '1' ext trigger on falling edge

BTE When set to '1' = Ext trigger on both edges

CAL If set to '1' unit does not use on board flash calibration.

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